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Electronics
Kerf vs EasyEDA
EasyEDA lowered the JLCPCB barrier to zero — Kerf raises the ceiling with in-box pre-compliance simulation.
22/22in Kerf today
8/22in EasyEDA (included)
3behind a paid tier
2026-05-24last reviewed
Grouped by discipline (D1–D14), same as Kerf's own capability list. Click a section to expand it.
D1 Geometry & core CAD
| Capability | Kerf | EasyEDA |
|---|---|---|
| MCAD/ECAD integration (co-resident) |
yes
packages/kerf-electronics/src/kerf_electronics/idf_roundtrip.py
|
no source ↗ |
D6 Electronics / EDA / silicon
| Capability | Kerf | EasyEDA |
|---|---|---|
| Schematic capture (KiCad round-trip, ERC) |
yes
packages/kerf-electronics/src/kerf_electronics/schematic/
|
yes source ↗ |
| PCB layout (tscircuit, KiCad round-trip) |
yes
packages/kerf-electronics/src/kerf_electronics/routing/
|
yes source ↗ |
| Interactive PCB editing (route/place) |
yes
packages/kerf-electronics/src/kerf_electronics/routing/
|
yes source ↗ |
| Autoroute (FreeRouting) |
yes
packages/kerf-electronics/src/kerf_electronics/freerouting/freerouting.py
|
paid tier source ↗ |
| SPICE |
yes
packages/kerf-electronics/src/kerf_electronics/spice/
|
yes source ↗ |
| Signal integrity (Z0/crosstalk/eye/IBIS) |
yes
packages/kerf-electronics/src/kerf_electronics/si/
|
paid tier source ↗ |
| EMC (radiated/shielding/limits) |
yes
packages/kerf-electronics/src/kerf_electronics/emc/
|
no source ↗ |
| PDN (DC IR-drop + AC sweep) |
yes
packages/kerf-electronics/src/kerf_electronics/pdn/
|
no source ↗ |
| PCB thermal |
yes
packages/kerf-electronics/src/kerf_electronics/thermal/
|
no source ↗ |
| DRC / ERC |
yes
packages/kerf-electronics/src/kerf_electronics/drc.py
|
yes source ↗ |
| Battery/BMS, motor/gate/LED driver |
yes
packages/kerf-electronics/src/kerf_electronics/battery/
|
no source ↗ |
| Antenna / link budget |
yes
packages/kerf-electronics/src/kerf_electronics/antenna/
|
no source ↗ |
| Silicon synth (Yosys) / STA / GDS / DRC / LVS / formal / CTS |
yes
packages/kerf-silicon/src/kerf_silicon/bridges/yosys_bridge.py
|
no source ↗ |
| Silicon P&R (OpenLane) |
yes
packages/kerf-silicon/src/kerf_silicon/openlane/
|
no source ↗ |
| Analog PVT-corner sim |
yes
packages/kerf-electronics/src/kerf_electronics/spice/corner_analysis.py
|
no source ↗ |
| Gerber / Excellon output |
yes
packages/kerf-electronics/src/kerf_electronics/fab/
|
yes source ↗ |
| IPC-2581 output |
yes
packages/kerf-electronics/src/kerf_electronics/fab/
|
no source ↗ |
| ODB++ output |
yes
packages/kerf-electronics/src/kerf_electronics/fab/
|
no source ↗ |
| Panelisation |
yes
packages/kerf-electronics/src/kerf_electronics/tools/panelize.py
|
paid tier source ↗ |
| JLCPCB / fab ordering integration |
yes
packages/kerf-electronics/src/kerf_electronics/fab/
|
yes source ↗ |
| Component library (LCSC-backed) |
yes
packages/kerf-electronics/src/kerf_electronics/tools/lib_mgmt.py
|
yes source ↗ |
- yes shipped
- partial works with limits
- paid tier present, but behind an add-on or meter
- no not available
Corrections welcome. These rows are read off published documentation on the date shown and go stale as products ship. If a row is wrong, open an issue — the source file is public/compare/easyeda.md and every claim in it carries a link.